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74f167cfdd
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Cleaned up comments
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2018-11-29 08:18:56 +01:00 |
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91f474c0e4
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Added software implementation
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2018-11-28 19:27:03 +01:00 |
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f4aa1a51d0
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Removed unused signals
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2018-11-28 18:23:49 +01:00 |
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b8dfb7c293
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Removed a few unused signals
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2018-11-28 18:16:44 +01:00 |
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0f462dfc9d
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Removed unused pin constraints
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2018-11-26 16:26:29 +01:00 |
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ce4abe0a1d
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Added VGA_ACTIVE signal
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2018-11-26 15:12:41 +01:00 |
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0621210322
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Fixed bug where x/y where not 0 indexed
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2018-11-25 20:47:30 +01:00 |
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7b64e027e8
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Cleanup of Verilog code
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2018-11-24 20:42:48 +01:00 |
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725c9a66e9
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Adding testbench
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2018-11-24 19:03:34 +01:00 |
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7095ad26df
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Removed version numbers from verilog modules, Fixed output for RGB so lines are low when there is no active drawing
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2018-11-21 12:21:28 +01:00 |
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95da9bf234
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Removed version numbers
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2018-11-20 19:45:37 +01:00 |
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1657c9f537
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Updated userland code
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2018-11-20 19:41:56 +01:00 |
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1d1217609e
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Added AXI interface
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2018-11-20 17:22:49 +01:00 |
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f65b8535e3
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Fixed typo and renamed some signals
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2018-11-19 20:59:35 +01:00 |
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7e569c41fe
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Added foreground and background color
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2018-11-11 18:55:56 +01:00 |
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2619c16c80
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Added diagram
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2018-11-11 13:26:19 +01:00 |
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7706c8b148
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Added constrain file with VGA pins on PMOD1
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2018-11-11 12:36:01 +01:00 |
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4ce52c4e2d
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Added parent module
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2018-11-11 12:10:40 +01:00 |
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22792c1300
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Original import
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2018-11-11 10:25:27 +01:00 |
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