Jens True ce4abe0a1d Added VGA_ACTIVE signal

2018-11-26 15:12:41 +01:00

.gitignore

Adding testbench

2018-11-24 19:03:34 +01:00

Makefile

Cleanup of Verilog code

2018-11-24 20:42:48 +01:00

minized_vga.xdc

Added AXI interface

2018-11-20 17:22:49 +01:00

overview.graphml

Fixed typo and renamed some signals

2018-11-19 20:59:35 +01:00

simplevga_S00_AXI.v

Removed version numbers from verilog modules, Fixed output for RGB so lines are low when there is no active drawing

2018-11-21 12:21:28 +01:00

simplevga.v

Added VGA_ACTIVE signal

2018-11-26 15:12:41 +01:00

userland.c

Updated userland code

2018-11-20 19:41:56 +01:00

vga640x480.v

Cleanup of Verilog code

2018-11-24 20:42:48 +01:00

vgasquare_tb.v

Added VGA_ACTIVE signal

2018-11-26 15:12:41 +01:00

vgasquare.v

Added VGA_ACTIVE signal

2018-11-26 15:12:41 +01:00

Description

FPGA implementation of a VGA driver Code from https://timetoexplore.net/blog/arty-fpga-vga-verilog-01

43 KiB

Languages

Verilog 57%

C 6.9%

Makefile 2.7%

Other 33.4%