Removed a few unused signals

vga640x480.v

@@ -1,7 +1,7 @@
 // FPGA VGA Graphics Part 1: 640x480 60Hz VGA Driver
 // (C)2017-2018 Will Green - Licensed under the MIT License
 // Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
-
+// Heavily modified by Jens True
 // For 60 Hz VGA i_pix_stb must be 25 MHz or 25.175 MHz
 // Details in tutorial: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
 
@@ -12,9 +12,7 @@ module vga640x480(
     input wire i_rst,           // reset: restarts frame
     output wire o_hs,           // horizontal sync
     output wire o_vs,           // vertical sync
-    output wire o_blanking,     // high during blanking interval
     output wire o_active,       // high during active pixel drawing
-    output wire o_screenend,    // high for one tick at the end of screen
     output wire o_animate,      // high for one tick at end of active drawing
     output wire [9:0] o_x,      // current pixel x position
     output wire [8:0] o_y       // current pixel y position
@@ -41,15 +39,9 @@ module vga640x480(
     assign o_x = (h_count < HA_STA) ? 0 : (h_count - HA_STA);
     assign o_y = (v_count >= VA_END) ? (VA_END - 1) : (v_count);
 
-    // blanking: high within the blanking period
-    assign o_blanking = ((h_count < HA_STA) | (v_count > VA_END - 1));
-
     // active: high during active pixel drawing
     assign o_active = ~((h_count < HA_STA) | (v_count > VA_END - 1)); 
 
-    // screenend: high for one tick at the end of the screen
-    assign o_screenend = ((v_count == SCREEN - 1) & (h_count == LINE));
-
     // animate: high for one tick at the end of the final active pixel line
     assign o_animate = ((v_count == VA_END - 1) & (h_count == LINE));