Jens True 2619c16c80 Added diagram

2018-11-11 13:26:19 +01:00

minized_vga.xdc

Added constrain file with VGA pins on PMOD1

2018-11-11 12:36:01 +01:00

overview.graphml

Added diagram

2018-11-11 13:26:19 +01:00

vga640x480.v

Original import

2018-11-11 10:25:27 +01:00

vgasquare.v

Added parent module

2018-11-11 12:10:40 +01:00

Description

FPGA implementation of a VGA driver Code from https://timetoexplore.net/blog/arty-fpga-vga-verilog-01

43 KiB

Languages

Verilog 57%

C 6.9%

Makefile 2.7%

Other 33.4%