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• bda1700d42 Realigned comments master Jens True 2018-11-30 20:13:28 +01:00
• 1898f5bffc Additional comments Jens True 2018-11-29 12:35:20 +01:00
• 74f167cfdd Cleaned up comments Jens True 2018-11-29 08:18:56 +01:00
• 91f474c0e4 Added software implementation Jens True 2018-11-28 19:27:03 +01:00
• f4aa1a51d0 Removed unused signals Jens True 2018-11-28 18:23:49 +01:00
• b8dfb7c293 Removed a few unused signals Jens True 2018-11-28 18:16:44 +01:00
• 0f462dfc9d Removed unused pin constraints Jens True 2018-11-26 16:26:29 +01:00
• ce4abe0a1d Added VGA_ACTIVE signal Jens True 2018-11-26 15:12:41 +01:00
• 0621210322 Fixed bug where x/y where not 0 indexed Jens True 2018-11-25 20:47:30 +01:00
• 7b64e027e8 Cleanup of Verilog code Jens True 2018-11-24 20:42:48 +01:00
• 725c9a66e9 Adding testbench Jens True 2018-11-24 19:03:34 +01:00
• 7095ad26df Removed version numbers from verilog modules, Fixed output for RGB so lines are low when there is no active drawing Jens True 2018-11-21 12:21:28 +01:00
• 95da9bf234 Removed version numbers Jens True 2018-11-20 19:45:37 +01:00
• 1657c9f537 Updated userland code Jens True 2018-11-20 19:41:56 +01:00
• 1d1217609e Added AXI interface Jens True 2018-11-20 17:22:49 +01:00
• f65b8535e3 Fixed typo and renamed some signals Jens True 2018-11-19 20:59:35 +01:00
• 7e569c41fe Added foreground and background color Jens True 2018-11-11 18:55:56 +01:00
• 2619c16c80 Added diagram Jens True 2018-11-11 13:26:19 +01:00
• 7706c8b148 Added constrain file with VGA pins on PMOD1 Jens True 2018-11-11 12:36:01 +01:00
• 4ce52c4e2d Added parent module Jens True 2018-11-11 12:10:40 +01:00
• 22792c1300 Original import Jens True 2018-11-11 10:25:27 +01:00