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f4aa1a51d0
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Removed unused signals
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2018-11-28 18:23:49 +01:00 |
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ce4abe0a1d
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Added VGA_ACTIVE signal
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2018-11-26 15:12:41 +01:00 |
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725c9a66e9
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Adding testbench
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2018-11-24 19:03:34 +01:00 |
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7095ad26df
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Removed version numbers from verilog modules, Fixed output for RGB so lines are low when there is no active drawing
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2018-11-21 12:21:28 +01:00 |
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95da9bf234
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Removed version numbers
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2018-11-20 19:45:37 +01:00 |
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