112 lines
3.7 KiB
Verilog
112 lines
3.7 KiB
Verilog
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`timescale 1 ns / 1 ps
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module simplevga #
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(
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// Users to add parameters here
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Parameters of Axi Slave Bus Interface S00_AXI
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parameter integer C_S00_AXI_DATA_WIDTH = 32,
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parameter integer C_S00_AXI_ADDR_WIDTH = 4
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)
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(
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// Users to add ports here
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input wire I_PIXEL_CLK,
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output wire O_VGA_ACTIVE, //High when drawing is active
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output wire O_VGA_HS, // horizontal sync output
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output wire O_VGA_VS, // vertical sync output
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output wire O_VGA_R, // 1-bit VGA red output
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output wire O_VGA_G, // 1-bit VGA green output
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output wire O_VGA_B, // 1-bit VGA blue output
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// User ports ends
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// Do not modify the ports beyond this line
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// Ports of Axi Slave Bus Interface S00_AXI
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input wire s00_axi_aclk,
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input wire s00_axi_aresetn,
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input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
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input wire [2 : 0] s00_axi_awprot,
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input wire s00_axi_awvalid,
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output wire s00_axi_awready,
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input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
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input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
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input wire s00_axi_wvalid,
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output wire s00_axi_wready,
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output wire [1 : 0] s00_axi_bresp,
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output wire s00_axi_bvalid,
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input wire s00_axi_bready,
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input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
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input wire [2 : 0] s00_axi_arprot,
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input wire s00_axi_arvalid,
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output wire s00_axi_arready,
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output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
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output wire [1 : 0] s00_axi_rresp,
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output wire s00_axi_rvalid,
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input wire s00_axi_rready
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);
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wire [C_S00_AXI_DATA_WIDTH-1:0] reg_x;
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wire [C_S00_AXI_DATA_WIDTH-1:0] reg_y;
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wire [C_S00_AXI_DATA_WIDTH-1:0] reg_color;
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// Instantiation of Axi Bus Interface S00_AXI
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simplevga_S00_AXI # (
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.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
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.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
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) simplevga_S00_AXI_inst (
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.slave_reg0(reg_x),
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.slave_reg1(reg_y),
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.slave_reg2(reg_color),
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.S_AXI_ACLK(s00_axi_aclk),
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.S_AXI_ARESETN(s00_axi_aresetn),
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.S_AXI_AWADDR(s00_axi_awaddr),
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.S_AXI_AWPROT(s00_axi_awprot),
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.S_AXI_AWVALID(s00_axi_awvalid),
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.S_AXI_AWREADY(s00_axi_awready),
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.S_AXI_WDATA(s00_axi_wdata),
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.S_AXI_WSTRB(s00_axi_wstrb),
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.S_AXI_WVALID(s00_axi_wvalid),
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.S_AXI_WREADY(s00_axi_wready),
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.S_AXI_BRESP(s00_axi_bresp),
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.S_AXI_BVALID(s00_axi_bvalid),
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.S_AXI_BREADY(s00_axi_bready),
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.S_AXI_ARADDR(s00_axi_araddr),
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.S_AXI_ARPROT(s00_axi_arprot),
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.S_AXI_ARVALID(s00_axi_arvalid),
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.S_AXI_ARREADY(s00_axi_arready),
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.S_AXI_RDATA(s00_axi_rdata),
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.S_AXI_RRESP(s00_axi_rresp),
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.S_AXI_RVALID(s00_axi_rvalid),
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.S_AXI_RREADY(s00_axi_rready)
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);
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// Add user logic here
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wire [9:0] box_x1 = reg_x[9:0];
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wire [9:0] box_x2 = reg_x[25:16];
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wire [8:0] box_y1 = reg_y[8:0];
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wire [8:0] box_y2 = reg_y[24:16];
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wire [5:0] box_color = reg_color[5:0];
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vgasquare display (
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.CLK(s00_axi_aclk), // board clock
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.PIXEL_CLK(I_PIXEL_CLK), // Pixel clock: 25Mhz (or 25.125MHz) for VGA
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.RST_BTN(s00_axi_aresetn), // reset button
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.box_x1(box_x1),
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.box_x2(box_x2),
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.box_y1(box_y1),
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.box_y2(box_y2),
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.box_color(box_color), //1 bit for each color Foreground and background
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.VGA_ACTIVE(O_VGA_ACTIVE),
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.VGA_HS(O_VGA_HS), // horizontal sync output
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.VGA_VS(O_VGA_VS), // vertical sync output
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.VGA_R(O_VGA_R), // 1-bit VGA red output
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.VGA_G(O_VGA_G), // 1-bit VGA green output
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.VGA_B(O_VGA_B) // 1-bit VGA blue output
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);
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// User logic ends
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endmodule
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