5 Commits

Author	SHA1	Message	Date
Jens True	f4aa1a51d0	Removed unused signals	2018-11-28 18:23:49 +01:00
Jens True	ce4abe0a1d	Added VGA_ACTIVE signal	2018-11-26 15:12:41 +01:00
Jens True	0621210322	Fixed bug where x/y where not 0 indexed	2018-11-25 20:47:30 +01:00
Jens True	7b64e027e8	Cleanup of Verilog code	2018-11-24 20:42:48 +01:00
Jens True	725c9a66e9	Adding testbench	2018-11-24 19:03:34 +01:00