33 lines
904 B
Verilog
33 lines
904 B
Verilog
`timescale 10ns/10ns
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module vgasquare_tb;
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// Make reset high
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reg reset = 1;
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initial begin
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$dumpfile("vgasquare_tb.vcd");
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$dumpvars;//(pixel_clk, pixel_clk, O_VGA_ACTIVE,O_VGA_HS, O_VGA_VS);
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#10000000 $finish;
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end
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//Make our pixel clock
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reg pixel_clk = 0;
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always #2 pixel_clk = !pixel_clk;
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wire O_VGA_ACTIVE;
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wire O_VGA_HS;
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wire O_VGA_VS;
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vgasquare display (
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.PIXEL_CLK(pixel_clk), // Pixel clock: 25Mhz (or 25.125MHz) for VGA
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.RST_BTN(reset), // reset button
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.box_x1(10'd120),
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.box_x2(10'd520),
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.box_y1(9'd120),
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.box_y2(9'd360),
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.box_color(6'b111000), //1 bit for each color Foreground and background
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.VGA_ACTIVE(O_VGA_ACTIVE),
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.VGA_HS(O_VGA_HS), // horizontal sync output
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.VGA_VS(O_VGA_VS) // vertical sync output
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);
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endmodule // test
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