7 Commits

Author	SHA1	Message	Date
Jens True	74f167cfdd	Cleaned up comments	2018-11-29 08:18:56 +01:00
Jens True	f4aa1a51d0	Removed unused signals	2018-11-28 18:23:49 +01:00
Jens True	b8dfb7c293	Removed a few unused signals	2018-11-28 18:16:44 +01:00
Jens True	7b64e027e8	Cleanup of Verilog code	2018-11-24 20:42:48 +01:00
Jens True	725c9a66e9	Adding testbench	2018-11-24 19:03:34 +01:00
Jens True	1d1217609e	Added AXI interface	2018-11-20 17:22:49 +01:00
Jens True	22792c1300	Original import	2018-11-11 10:25:27 +01:00