jct/vga640x480
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Removed unused signals

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This commit is contained in:
Jens True
2018-11-28 18:23:49 +01:00
parent b8dfb7c293
commit f4aa1a51d0
4 changed files with 14 additions and 15 deletions
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2
simplevga.v
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@ -91,7 +91,7 @@
vgasquare display ( vgasquare display (
.PIXEL_CLK(I_PIXEL_CLK), // Pixel clock: 25Mhz (or 25.125MHz) for VGA .PIXEL_CLK(I_PIXEL_CLK), // Pixel clock: 25Mhz (or 25.125MHz) for VGA
.RST_BTN(s00_axi_aresetn), // reset button .RESET(s00_axi_aresetn), // Reset Signal
.box_x1(box_x1), .box_x1(box_x1),
.box_x2(box_x2), .box_x2(box_x2),
.box_y1(box_y1), .box_y1(box_y1),

4
vga640x480.v
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@ -2,7 +2,7 @@
// (C)2017-2018 Will Green - Licensed under the MIT License // (C)2017-2018 Will Green - Licensed under the MIT License
// Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 // Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
// Heavily modified by Jens True // Heavily modified by Jens True
// For 60 Hz VGA i_pix_stb must be 25 MHz or 25.175 MHz // For 60 Hz VGA i_pix_stb must beg 25 MHz or 25.175 MHz
// Details in tutorial: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 // Details in tutorial: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
`default_nettype none `default_nettype none
@ -47,7 +47,7 @@ module vga640x480(
always @ (posedge i_pix_stb) always @ (posedge i_pix_stb)
begin begin
if (i_rst) // reset to start of frame if (~i_rst) // reset to start of frame- Reset is active low on AXI bus so here we intervert it
begin begin
h_count <= 0; h_count <= 0;
v_count <= 0; v_count <= 0;

9
vgasquare.v
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@ -7,7 +7,7 @@
module vgasquare( module vgasquare(
input wire PIXEL_CLK, // Pixel clock: 25Mhz (or 25.125MHz) for VGA input wire PIXEL_CLK, // Pixel clock: 25Mhz (or 25.125MHz) for VGA
input wire RST_BTN, // reset button input wire RESET, // Reset signal
input wire [9:0] box_x1, input wire [9:0] box_x1,
input wire [9:0] box_x2, input wire [9:0] box_x2,
input wire [8:0] box_y1, input wire [8:0] box_y1,
@ -20,14 +20,12 @@ module vgasquare(
output wire VGA_B // 1-bit VGA blue output output wire VGA_B // 1-bit VGA blue output
); );
wire rst = ~RST_BTN; // reset is active low on AXI bus
wire [9:0] x; // current pixel x position: 10-bit value: 0-1023 wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
wire [8:0] y; // current pixel y position: 9-bit value: 0-511 wire [8:0] y; // current pixel y position: 9-bit value: 0-511
wire VGA_ACTIVE; wire VGA_ACTIVE; // Internal signal
vga640x480 display ( vga640x480 display (
.i_pix_stb(PIXEL_CLK), .i_pix_stb(PIXEL_CLK),
.i_rst(rst), .i_rst(RESET),
.o_hs(VGA_HS), .o_hs(VGA_HS),
.o_vs(VGA_VS), .o_vs(VGA_VS),
.o_active(VGA_ACTIVE), .o_active(VGA_ACTIVE),
@ -40,6 +38,7 @@ module vgasquare(
wire R = square ? box_color[0] : box_color[3]; wire R = square ? box_color[0] : box_color[3];
wire G = square ? box_color[1] : box_color[4]; wire G = square ? box_color[1] : box_color[4];
wire B = square ? box_color[2] : box_color[5]; wire B = square ? box_color[2] : box_color[5];
assign VGA_R = VGA_ACTIVE ? R : 0; // Set R (Foreground and then background) assign VGA_R = VGA_ACTIVE ? R : 0; // Set R (Foreground and then background)
assign VGA_G = VGA_ACTIVE ? G : 0; // Set G assign VGA_G = VGA_ACTIVE ? G : 0; // Set G
assign VGA_B = VGA_ACTIVE ? B : 0; // Set B assign VGA_B = VGA_ACTIVE ? B : 0; // Set B

2
vgasquare_tb.v
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@ -20,7 +20,7 @@ module vgasquare_tb;
vgasquare DUT ( vgasquare DUT (
.PIXEL_CLK(pixel_clk), // Pixel clock: 25Mhz (or 25.125MHz) for VGA .PIXEL_CLK(pixel_clk), // Pixel clock: 25Mhz (or 25.125MHz) for VGA
.RST_BTN(reset), // reset button .RESET(reset), // reset button
.box_x1(10'd1), .box_x1(10'd1),
.box_x2(10'd2), .box_x2(10'd2),
.box_y1(9'd1), .box_y1(9'd1),