From f4aa1a51d0360c7b95457f1de8f9555df8b6aef3 Mon Sep 17 00:00:00 2001 From: Jens True Date: Wed, 28 Nov 2018 18:23:49 +0100 Subject: [PATCH] Removed unused signals --- simplevga.v | 2 +- vga640x480.v | 4 ++-- vgasquare.v | 19 +++++++++---------- vgasquare_tb.v | 4 ++-- 4 files changed, 14 insertions(+), 15 deletions(-) diff --git a/simplevga.v b/simplevga.v index a9d42a0..651f521 100644 --- a/simplevga.v +++ b/simplevga.v @@ -91,7 +91,7 @@ vgasquare display ( .PIXEL_CLK(I_PIXEL_CLK), // Pixel clock: 25Mhz (or 25.125MHz) for VGA - .RST_BTN(s00_axi_aresetn), // reset button + .RESET(s00_axi_aresetn), // Reset Signal .box_x1(box_x1), .box_x2(box_x2), .box_y1(box_y1), diff --git a/vga640x480.v b/vga640x480.v index f3df579..b46b62b 100644 --- a/vga640x480.v +++ b/vga640x480.v @@ -2,7 +2,7 @@ // (C)2017-2018 Will Green - Licensed under the MIT License // Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 // Heavily modified by Jens True -// For 60 Hz VGA i_pix_stb must be 25 MHz or 25.175 MHz +// For 60 Hz VGA i_pix_stb must beg 25 MHz or 25.175 MHz // Details in tutorial: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01 `default_nettype none @@ -47,7 +47,7 @@ module vga640x480( always @ (posedge i_pix_stb) begin - if (i_rst) // reset to start of frame + if (~i_rst) // reset to start of frame- Reset is active low on AXI bus so here we intervert it begin h_count <= 0; v_count <= 0; diff --git a/vgasquare.v b/vgasquare.v index 653f029..fd1f55d 100644 --- a/vgasquare.v +++ b/vgasquare.v @@ -7,27 +7,25 @@ module vgasquare( input wire PIXEL_CLK, // Pixel clock: 25Mhz (or 25.125MHz) for VGA - input wire RST_BTN, // reset button + input wire RESET, // Reset signal input wire [9:0] box_x1, input wire [9:0] box_x2, input wire [8:0] box_y1, input wire [8:0] box_y2, input wire [5:0] box_color, //1 bit for each color Foreground and background - output wire VGA_HS, // horizontal sync output - output wire VGA_VS, // vertical sync output - output wire VGA_R, // 1-bit VGA red output + output wire VGA_HS, // horizontal sync output + output wire VGA_VS, // vertical sync output + output wire VGA_R, // 1-bit VGA red output output wire VGA_G, // 1-bit VGA green output output wire VGA_B // 1-bit VGA blue output ); - wire rst = ~RST_BTN; // reset is active low on AXI bus - - wire [9:0] x; // current pixel x position: 10-bit value: 0-1023 - wire [8:0] y; // current pixel y position: 9-bit value: 0-511 - wire VGA_ACTIVE; + wire [9:0] x; // current pixel x position: 10-bit value: 0-1023 + wire [8:0] y; // current pixel y position: 9-bit value: 0-511 + wire VGA_ACTIVE; // Internal signal vga640x480 display ( .i_pix_stb(PIXEL_CLK), - .i_rst(rst), + .i_rst(RESET), .o_hs(VGA_HS), .o_vs(VGA_VS), .o_active(VGA_ACTIVE), @@ -40,6 +38,7 @@ module vgasquare( wire R = square ? box_color[0] : box_color[3]; wire G = square ? box_color[1] : box_color[4]; wire B = square ? box_color[2] : box_color[5]; + assign VGA_R = VGA_ACTIVE ? R : 0; // Set R (Foreground and then background) assign VGA_G = VGA_ACTIVE ? G : 0; // Set G assign VGA_B = VGA_ACTIVE ? B : 0; // Set B diff --git a/vgasquare_tb.v b/vgasquare_tb.v index ebc5cd8..678d14b 100644 --- a/vgasquare_tb.v +++ b/vgasquare_tb.v @@ -20,8 +20,8 @@ module vgasquare_tb; vgasquare DUT ( .PIXEL_CLK(pixel_clk), // Pixel clock: 25Mhz (or 25.125MHz) for VGA - .RST_BTN(reset), // reset button - .box_x1(10'd1), + .RESET(reset), // reset button + .box_x1(10'd1), .box_x2(10'd2), .box_y1(9'd1), .box_y2(9'd2),