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Added VGA_ACTIVE signal

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Jens True
2018-11-26 15:12:41 +01:00
parent 0621210322
commit ce4abe0a1d
3 changed files with 2 additions and 6 deletions
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2
simplevga.v
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@@ -16,7 +16,6 @@
(
// Users to add ports here
input wire I_PIXEL_CLK,
output wire O_VGA_ACTIVE, //High when drawing is active
output wire O_VGA_HS, // horizontal sync output
output wire O_VGA_VS, // vertical sync output
output wire O_VGA_R, // 1-bit VGA red output
@@ -98,7 +97,6 @@
.box_y1(box_y1),
.box_y2(box_y2),
.box_color(box_color), //1 bit for each color Foreground and background
.VGA_ACTIVE(O_VGA_ACTIVE),
.VGA_HS(O_VGA_HS), // horizontal sync output
.VGA_VS(O_VGA_VS), // vertical sync output
.VGA_R(O_VGA_R), // 1-bit VGA red output

3
vgasquare.v
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@@ -13,7 +13,6 @@ module vgasquare(
input wire [8:0] box_y1,
input wire [8:0] box_y2,
input wire [5:0] box_color, //1 bit for each color Foreground and background
output wire VGA_ACTIVE, //High when drawing is active
output wire VGA_HS, // horizontal sync output
output wire VGA_VS, // vertical sync output
output wire VGA_R, // 1-bit VGA red output
@@ -25,7 +24,7 @@ module vgasquare(
wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
wire [8:0] y; // current pixel y position: 9-bit value: 0-511
wire VGA_ACTIVE;
vga640x480 display (
.i_pix_stb(PIXEL_CLK),
.i_rst(rst),

3
vgasquare_tb.v
View File

@@ -5,7 +5,7 @@ module vgasquare_tb;
reg reset = 1;
initial begin
$dumpfile("vgasquare_tb.vcd");
$dumpvars;//(pixel_clk, pixel_clk, O_VGA_ACTIVE,O_VGA_HS, O_VGA_VS);
$dumpvars;
#16800000 $finish;
end
@@ -26,7 +26,6 @@ module vgasquare_tb;
.box_y1(9'd1),
.box_y2(9'd2),
.box_color(6'b100001), //1 bit for each color Foreground and background
.VGA_ACTIVE(O_VGA_ACTIVE),
.VGA_HS(O_VGA_HS), // horizontal sync output
.VGA_VS(O_VGA_VS), // vertical sync output
.VGA_R(O_VGA_R), // 1-bit VGA red output