Adding testbench

.gitignore

@@ -0,0 +1,3 @@
+*.vpp
+*.vcd
+*.out

Makefile

@@ -0,0 +1,36 @@
+TESTBENCH = vgasquare_tb.v
+SRC = vgasquare.v vga640x480.v
+
+#Tools
+COMPILER = "C:\System\iverilog\bin\iverilog.exe"
+SIMULATOR = "C:\System\iverilog\bin\vvp.exe"
+VIEWER = "C:\System\iverilog\gtkwave\bin\gtkwave.exe"
+
+TBOUTPUT = vgasquare_tb.vcd	#THIS NEEDS TO MATCH THE OUTPUT FILE
+							#FROM YOUR TESTBENCH
+###############################################################################
+# BE CAREFUL WHEN CHANGING ITEMS BELOW THIS LINE
+###############################################################################
+#TOOL OPTIONS
+COFLAGS =  -o
+SFLAGS = 
+SOUTPUT = -lxt		#SIMULATOR OUTPUT TYPE
+#TOOL OUTPUT
+COUTPUT = vgasquare_tb.vpp			#COMPILER OUTPUT
+###############################################################################
+#MAKE DIRECTIVES
+check : $(TESTBENCH) $(SRC)
+	$(COMPILER) -v $(SRC)
+
+simulate: $(COUTPUT)
+	$(SIMULATOR) $(SFLAGS) $(COUTPUT) $(SOUTPUT)
+
+display: $(TBOUTPUT)
+	$(VIEWER) $(TBOUTPUT)
+
+#MAKE DEPENDANCIES
+$(TBOUTPUT): $(COUTPUT)
+	$(SIMULATOR) $(SOPTIONS) $(COUTPUT) $(SOUTPUT)
+
+$(COUTPUT): $(TESTBENCH) $(SRC)
+	$(COMPILER) $(COFLAGS) $(COUTPUT) $(TESTBENCH) $(SRC)

simplevga.v

@@ -91,7 +91,6 @@
     wire [5:0] box_color = reg_color[5:0];
     
     vgasquare display ( 
-        .CLK(s00_axi_aclk),             // board clock
         .PIXEL_CLK(I_PIXEL_CLK),       // Pixel clock: 25Mhz (or 25.125MHz) for VGA
         .RST_BTN(s00_axi_aresetn),         // reset button
         .box_x1(box_x1),

vga640x480.v

@@ -8,7 +8,6 @@
 `default_nettype none
 
 module vga640x480(
-    input wire i_clk,           // base clock
     input wire i_pix_stb,       // pixel clock strobe
     input wire i_rst,           // reset: restarts frame
     output wire o_hs,           // horizontal sync

vgasquare.v

@@ -6,7 +6,6 @@
 `default_nettype none
 
 module vgasquare(
-    input wire CLK,             // board clock
 	input wire PIXEL_CLK,       // Pixel clock: 25Mhz (or 25.125MHz) for VGA
     input wire RST_BTN,         // reset button
 	input wire [9:0] box_x1,
@@ -28,7 +27,6 @@ module vgasquare(
     wire [8:0] y;  // current pixel y position:  9-bit value: 0-511
 
     vga640x480 display (
-        .i_clk(CLK),
         .i_pix_stb(PIXEL_CLK),
         .i_rst(rst),
         .o_active(VGA_ACTIVE),

vgasquare_tb.v

@@ -0,0 +1,33 @@
+`timescale 10ns/10ns
+module vgasquare_tb;
+
+  // Make reset high
+  reg reset = 1;
+  initial begin
+     $dumpfile("vgasquare_tb.vcd");
+     $dumpvars;//(pixel_clk, pixel_clk, O_VGA_ACTIVE,O_VGA_HS, O_VGA_VS);
+     #10000000 $finish;
+  end
+
+
+  //Make our pixel clock
+  reg pixel_clk = 0;
+  always #2 pixel_clk = !pixel_clk;
+  
+  wire O_VGA_ACTIVE;
+  wire O_VGA_HS;
+  wire O_VGA_VS;
+
+  vgasquare display ( 
+        .PIXEL_CLK(pixel_clk),       // Pixel clock: 25Mhz (or 25.125MHz) for VGA
+        .RST_BTN(reset),         // reset button
+        .box_x1(10'd120),
+        .box_x2(10'd520),
+        .box_y1(9'd120),
+        .box_y2(9'd360),    
+        .box_color(6'b111000),      //1 bit for each color  Foreground and background
+        .VGA_ACTIVE(O_VGA_ACTIVE),
+        .VGA_HS(O_VGA_HS),       // horizontal sync output
+        .VGA_VS(O_VGA_VS)       // vertical sync output
+        );
+endmodule // test