REG_DMM Union Reference

Represents a Display Memory Mode value. More...

#include <max7456Registers.h>

Public Attributes
unsigned char	whole
	The whole register value.
struct {
unsigned char   autoIncrementMode: 1
	Auto-Increment Mode.
unsigned char   verticalSynchClear: 1
	Vertical Sync Clear (Valid only when clear display memory = 1, (DMM[2] = 1) )
unsigned char   clearDisplayMemory: 1
	Clear Display Memory.
unsigned char   INV: 1
	Invert Bit (applies to characters written in 16-bit operating mode)
unsigned char   BLK: 1
	Blink Bit (applies to characters written in 16-bit operating mode)
unsigned char   LBC: 1
	Local Background Control Bit (applies to characters written in 16-bit operating mode)
unsigned char   operationModeSelection: 1
	Operation Mode Selection.
unsigned char   unsused: 1
	Don't care.
}	bits
	access to individual bits

Detailed Description

Represents a Display Memory Mode value.

Member Data Documentation

unsigned char REG_DMM::autoIncrementMode

Auto-Increment Mode.

• 0 = Disabled
• 1 = Enabled

  Note

  When this bit is enabled for the first time, data in the Display Memory Address (DMAH[0] and DMAL[7:0]) registers are used as the starting location to which the data is written. When performing the auto-increment write for the display memory, the 8-bit address is internally generated, and therefore only 8-bit data is required by the SPI-compatible interface (Figure 21). The content is to be interpreted as a Character Address byte if DMAH[1] = 0 or a Character Attribute byte if DMAH[1] = 1. This mode is disabled by writing the escape character 1111 1111. If the Clear Display Memory bit is set, this bit is reset internally.

REG_DMM::bits

access to individual bits

unsigned char REG_DMM::BLK

Blink Bit (applies to characters written in 16-bit operating mode)

• 0 = Blinking off
• 1 = Blinking on

  Note

  Blinking rate and blinking duty cycle data in the Video Mode 1 (VM1) register are used for blinking control

unsigned char REG_DMM::clearDisplayMemory

Clear Display Memory.

• 0 = Inactive
• 1 = Clear (fill all display memories with zeros)

  Note

  This bit is automatically cleared after the operation is completed (the operation requires 20us). The user does not need to write a 0 afterwards. The status of the bit can be checked by reading this register. This operation is automatically performed: a) On power-up b) Immediately following the rising edge of RESET c) Immediately following the rising edge of CS after VM0[1] has been set to 1

unsigned char REG_DMM::INV

Invert Bit (applies to characters written in 16-bit operating mode)

• 0 = Normal (white pixels display white, black pixels display black)
• 1 = Invert (white pixels display black, black pixels display white)

unsigned char REG_DMM::LBC

Local Background Control Bit (applies to characters written in 16-bit operating mode)

• 0 = sets the background pixels of the character to the video input (VIN) when in external sync mode.
• 1 = sets the background pixels of the character to the background mode brightness level defined by VM1[6:4] in external or internal sync mode.

  Note

  In internal sync mode, the local background control bit behaves as if it is set to 1

unsigned char REG_DMM::operationModeSelection

Operation Mode Selection.

• 0 = 16-bit operation mode
• 1 = 8-bit operation mode

unsigned char REG_DMM::unsused

Don't care.

unsigned char REG_DMM::verticalSynchClear

Vertical Sync Clear (Valid only when clear display memory = 1, (DMM[2] = 1) )

• 0 = Immediately applies the clear display-memory command, DMM[2] = 1
• 1 = Applies the clear display-memory command, DMM[2] = 1, at the next VSYNC time

unsigned char REG_DMM::whole

The whole register value.

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The documentation for this union was generated from the following file:

• max7456Registers.h