Jens True bda1700d42 Realigned comments

2018-11-30 20:13:28 +01:00

.gitignore

Adding testbench

2018-11-24 19:03:34 +01:00

helloworld.c

Added software implementation

2018-11-28 19:27:03 +01:00

Makefile

Cleanup of Verilog code

2018-11-24 20:42:48 +01:00

minized_vga.xdc

Removed unused pin constraints

2018-11-26 16:26:29 +01:00

overview.graphml

Fixed typo and renamed some signals

2018-11-19 20:59:35 +01:00

simplevga_S00_AXI.v

Removed version numbers from verilog modules, Fixed output for RGB so lines are low when there is no active drawing

2018-11-21 12:21:28 +01:00

simplevga.v

Realigned comments

2018-11-30 20:13:28 +01:00

vga640x480.v

Cleaned up comments

2018-11-29 08:18:56 +01:00

vgasquare_tb.v

Removed unused signals

2018-11-28 18:23:49 +01:00

vgasquare.v

Additional comments

2018-11-29 12:35:20 +01:00

Description

FPGA implementation of a VGA driver Code from https://timetoexplore.net/blog/arty-fpga-vga-verilog-01

43 KiB

Languages

Verilog 57%

C 6.9%

Makefile 2.7%

Other 33.4%