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Removed version numbers from verilog modules, Fixed output for RGB so lines are low when there is no active drawing

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This commit is contained in:
Jens True
2018-11-21 12:21:28 +01:00
parent 95da9bf234
commit 7095ad26df
3 changed files with 10 additions and 9 deletions
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6
simplevga.v
View File

@ -1,7 +1,7 @@
`timescale 1 ns / 1 ps
module simplevga_v1_0 #
module simplevga #
(
// Users to add parameters here
@ -53,10 +53,10 @@
wire [C_S00_AXI_DATA_WIDTH-1:0] reg_y;
wire [C_S00_AXI_DATA_WIDTH-1:0] reg_color;
// Instantiation of Axi Bus Interface S00_AXI
simplevga_v1_0_S00_AXI # (
simplevga_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) simplevga_v1_0_S00_AXI_inst (
) simplevga_S00_AXI_inst (
.slave_reg0(reg_x),
.slave_reg1(reg_y),
.slave_reg2(reg_color),

2
simplevga_S00_AXI.v
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@ -1,7 +1,7 @@
`timescale 1 ns / 1 ps
module simplevga_v1_0_S00_AXI #
module simplevga_S00_AXI #
(
// Users to add parameters here

11
vgasquare.v
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@ -40,9 +40,10 @@ module vgasquare(
// Draw one square
wire square = ((x > box_x1) & (y > box_y1) & (x < box_x2) & (y < box_y2)) ? 1 : 0; //Is box within range?
assign VGA_R = square ? box_color[0] : box_color[3]; // Set R (Foreground and then background)
assign VGA_G = square ? box_color[1] : box_color[4]; // Set G
assign VGA_B = square ? box_color[2] : box_color[5]; // Set B
wire R = square ? box_color[0] : box_color[3];
wire G = square ? box_color[1] : box_color[4];
wire B = square ? box_color[2] : box_color[5];
assign VGA_R = VGA_ACTIVE ? R : 0; // Set R (Foreground and then background)
assign VGA_G = VGA_ACTIVE ? G : 0; // Set G
assign VGA_B = VGA_ACTIVE ? B : 0; // Set B
endmodule