53 lines
1.7 KiB
Coq
53 lines
1.7 KiB
Coq
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// FPGA VGA Graphics Part 1: Top Module (static squares)
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// (C)2017-2018 Will Green - Licensed under the MIT License
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// Heavily modified by Jens True
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// Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
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`default_nettype none
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module vgasquare(
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input wire CLK, // board clock: 100 MHz clock in required
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input wire RST_BTN, // reset button
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input wire [9:0] box_x1,
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input wire [9:0] box_x2,
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input wire [8:0] box_y1,
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input wire [8:0] box_y2,
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input wire [2:0] box_color, //1 bit for each color
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output wire VGA_HS_O, // horizontal sync output
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output wire VGA_VS_O, // vertical sync output
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output wire VGA_R, // 1-bit VGA red output
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output wire VGA_G, // 1-bit VGA green output
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output wire VGA_B // 1-bit VGA blue output
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);
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wire rst = ~RST_BTN; // reset is active low on AXI bus
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// generate a 25 MHz pixel strobe
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reg [15:0] cnt;
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reg pix_stb;
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always @(posedge CLK)
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{pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000
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wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
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wire [8:0] y; // current pixel y position: 9-bit value: 0-511
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vga640x480 display (
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.i_clk(CLK),
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.i_pix_stb(pix_stb),
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.i_rst(rst),
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.o_hs(VGA_HS_O),
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.o_vs(VGA_VS_O),
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.o_x(x),
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.o_y(y)
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);
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// Draw one square
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wire square;
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assign square = ((x > box_x1) & (y > box_y1) & (x < box_x2) & (y < box_y1)) ? 1 : 0; //Is box within range?
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assign VGA_R = square ? box_color[0] : 0; // Set R
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assign VGA_G = square ? box_color[1] : 0 // Set G
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assign VGA_B = square ? box_color[2] : 0 // Set B
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endmodule
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