vga640x480/userland.c
2018-11-20 19:41:56 +01:00

74 lines
2.9 KiB
C

/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
*
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* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
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* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
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*
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******************************************************************************/
/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/
#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xil_io.h"
#include <simplevga.h>
int main()
{
init_platform();
print("Hello World\n\r");
SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG0_OFFSET, 0xFFFFFFFF);
SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG1_OFFSET, 0xFFFFFFFF);
SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG2_OFFSET, 0xFFFFFFFF);
unsigned long x = 1;
while(1) {
for(x = 1; x < 100; x++) {
unsigned long xreg = ((640-x) << 16) + x;
SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG0_OFFSET, x);
sleep(1);
}
}
cleanup_platform();
return 0;
}