46 lines
1.8 KiB
Verilog
46 lines
1.8 KiB
Verilog
// FPGA VGA Graphics Part 1: Top Module (static squares)
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// (C)2017-2018 Will Green - Licensed under the MIT License
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// Heavily modified by Jens True
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// Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
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`default_nettype none
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module vgasquare(
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input wire PIXEL_CLK, // Pixel clock: 25Mhz (or 25.125MHz) for VGA
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input wire RESET, // Reset signal
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input wire [9:0] box_x1,
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input wire [9:0] box_x2,
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input wire [8:0] box_y1,
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input wire [8:0] box_y2,
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input wire [5:0] box_color, //1 bit for each color Foreground and background
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output wire VGA_HS, // horizontal sync output
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output wire VGA_VS, // vertical sync output
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output wire VGA_R, // 1-bit VGA red output
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output wire VGA_G, // 1-bit VGA green output
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output wire VGA_B // 1-bit VGA blue output
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);
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wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
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wire [8:0] y; // current pixel y position: 9-bit value: 0-511
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wire VGA_ACTIVE; // Internal signal, color signals need to be low when not actively drawing.
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vga640x480 display (
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.i_pix_stb(PIXEL_CLK),
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.i_rst(RESET),
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.o_hs(VGA_HS),
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.o_vs(VGA_VS),
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.o_active(VGA_ACTIVE),
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.o_x(x),
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.o_y(y)
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);
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// Draw one square
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wire square = ((x >= box_x1) & (y >= box_y1) & (x <= box_x2) & (y <= box_y2)) ? 1 : 0; //Is box within range?
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wire R = square ? box_color[0] : box_color[3];
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wire G = square ? box_color[1] : box_color[4];
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wire B = square ? box_color[2] : box_color[5];
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assign VGA_R = VGA_ACTIVE ? R : 0; // Set R (Foreground and then background)
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assign VGA_G = VGA_ACTIVE ? G : 0; // Set G
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assign VGA_B = VGA_ACTIVE ? B : 0; // Set B
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endmodule
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