// FPGA VGA Graphics Part 1: Top Module (static squares)
// (C)2017-2018 Will Green - Licensed under the MIT License
// Heavily modified by Jens True
// Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01

`default_nettype none

module vgasquare(
	input wire PIXEL_CLK,       // Pixel clock: 25Mhz (or 25.125MHz) for VGA
    input wire RESET,           // Reset signal
	input wire [9:0] box_x1,
	input wire [9:0] box_x2,
	input wire [8:0] box_y1,
	input wire [8:0] box_y2,    
	input wire [5:0] box_color, // 1 bit for each color RGB  Foreground (bit 0,1 and 2) and background (bit 3,4 and 5)
    output wire VGA_HS,         // horizontal sync output
    output wire VGA_VS,         // vertical sync output
    output wire VGA_R,    	    // 1-bit VGA red output
    output wire VGA_G,    		// 1-bit VGA green output
    output wire VGA_B     		// 1-bit VGA blue output
    );

    wire [9:0] x;               // current pixel x position: 10-bit value: 0-1023
    wire [8:0] y;               // current pixel y position:  9-bit value: 0-511
    wire VGA_ACTIVE;            // Internal signal, color signals need to be low when not actively drawing.
    vga640x480 display (
        .i_pix_stb(PIXEL_CLK),
        .i_rst(RESET),
        .o_hs(VGA_HS), 
        .o_vs(VGA_VS), 
        .o_active(VGA_ACTIVE),
        .o_x(x), 
        .o_y(y)
    );

    // Draw one square
    wire square = ((x >= box_x1) & (y >=  box_y1) & (x <= box_x2) & (y <= box_y2)) ? 1 : 0; //Is box within range?
    wire R = square ? box_color[0] : box_color[3];
    wire G = square ? box_color[1] : box_color[4];
    wire B = square ? box_color[2] : box_color[5];

    assign VGA_R = VGA_ACTIVE ? R : 0;	// Set R (Foreground and then background) 
    assign VGA_G = VGA_ACTIVE ? G : 0;	// Set G
    assign VGA_B = VGA_ACTIVE ? B : 0;	// Set B
endmodule