`timescale 1 ns / 1 ps

	module simplevga #
	(
		// Users to add parameters here

		// User parameters ends
		// Do not modify the parameters beyond this line


		// Parameters of Axi Slave Bus Interface S00_AXI
		parameter integer C_S00_AXI_DATA_WIDTH	= 32,
		parameter integer C_S00_AXI_ADDR_WIDTH	= 4
	)
	(
		// Users to add ports here
        input  wire I_PIXEL_CLK,
        output wire O_VGA_HS,       // horizontal sync output
        output wire O_VGA_VS,       // vertical sync output
        output wire O_VGA_R,            // 1-bit VGA red output
        output wire O_VGA_G,            // 1-bit VGA green output
        output wire O_VGA_B,             // 1-bit VGA blue output
		// User ports ends
		// Do not modify the ports beyond this line


		// Ports of Axi Slave Bus Interface S00_AXI
		input wire  s00_axi_aclk,
		input wire  s00_axi_aresetn,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
		input wire [2 : 0] s00_axi_awprot,
		input wire  s00_axi_awvalid,
		output wire  s00_axi_awready,
		input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
		input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
		input wire  s00_axi_wvalid,
		output wire  s00_axi_wready,
		output wire [1 : 0] s00_axi_bresp,
		output wire  s00_axi_bvalid,
		input wire  s00_axi_bready,
		input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
		input wire [2 : 0] s00_axi_arprot,
		input wire  s00_axi_arvalid,
		output wire  s00_axi_arready,
		output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
		output wire [1 : 0] s00_axi_rresp,
		output wire  s00_axi_rvalid,
		input wire  s00_axi_rready
	);
	wire [C_S00_AXI_DATA_WIDTH-1:0] reg_x;
	wire [C_S00_AXI_DATA_WIDTH-1:0] reg_y;
	wire [C_S00_AXI_DATA_WIDTH-1:0] reg_color;
// Instantiation of Axi Bus Interface S00_AXI
	simplevga_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
		.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
	) simplevga_S00_AXI_inst (
	    .slave_reg0(reg_x),
	    .slave_reg1(reg_y),
	    .slave_reg2(reg_color),
		.S_AXI_ACLK(s00_axi_aclk),
		.S_AXI_ARESETN(s00_axi_aresetn),
		.S_AXI_AWADDR(s00_axi_awaddr),
		.S_AXI_AWPROT(s00_axi_awprot),
		.S_AXI_AWVALID(s00_axi_awvalid),
		.S_AXI_AWREADY(s00_axi_awready),
		.S_AXI_WDATA(s00_axi_wdata),
		.S_AXI_WSTRB(s00_axi_wstrb),
		.S_AXI_WVALID(s00_axi_wvalid),
		.S_AXI_WREADY(s00_axi_wready),
		.S_AXI_BRESP(s00_axi_bresp),
		.S_AXI_BVALID(s00_axi_bvalid),
		.S_AXI_BREADY(s00_axi_bready),
		.S_AXI_ARADDR(s00_axi_araddr),
		.S_AXI_ARPROT(s00_axi_arprot),
		.S_AXI_ARVALID(s00_axi_arvalid),
		.S_AXI_ARREADY(s00_axi_arready),
		.S_AXI_RDATA(s00_axi_rdata),
		.S_AXI_RRESP(s00_axi_rresp),
		.S_AXI_RVALID(s00_axi_rvalid),
		.S_AXI_RREADY(s00_axi_rready)
	);

	// Add user logic here
    wire [9:0] box_x1 = reg_x[9:0];
    wire [9:0] box_x2 = reg_x[25:16];
    wire [8:0] box_y1 = reg_y[8:0];
    wire [8:0] box_y2 = reg_y[24:16];
    wire [5:0] box_color = reg_color[5:0];
    
    vgasquare display ( 
        .PIXEL_CLK(I_PIXEL_CLK),       // Pixel clock: 25Mhz (or 25.125MHz) for VGA
        .RESET(s00_axi_aresetn),       // Reset Signal
        .box_x1(box_x1),
        .box_x2(box_x2),
        .box_y1(box_y1),
        .box_y2(box_y2),    
        .box_color(box_color),      //1 bit for each color  Foreground and background
        .VGA_HS(O_VGA_HS),       	// horizontal sync output
        .VGA_VS(O_VGA_VS),       	// vertical sync output
        .VGA_R(O_VGA_R),            // 1-bit VGA red output
        .VGA_G(O_VGA_G),            // 1-bit VGA green output
        .VGA_B(O_VGA_B)             // 1-bit VGA blue output
        );
	// User logic ends

	endmodule