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Cleanup of Verilog code

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This commit is contained in:
Jens True 2018-11-24 20:42:48 +01:00
parent 725c9a66e9
commit 7b64e027e8
4 changed files with 13 additions and 10 deletions
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2
Makefile
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@ -20,7 +20,7 @@ COUTPUT = vgasquare_tb.vpp #COMPILER OUTPUT
###############################################################################
#MAKE DIRECTIVES
check : $(TESTBENCH) $(SRC)
$(COMPILER) -v $(SRC)
$(COMPILER) $(SRC)
simulate: $(COUTPUT)
$(SIMULATOR) $(SFLAGS) $(COUTPUT) $(SOUTPUT)

4
vga640x480.v
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@ -30,8 +30,8 @@ module vga640x480(
localparam LINE = 800; // complete line (pixels)
localparam SCREEN = 524; // complete screen (lines)
reg [9:0] h_count; // line position
reg [9:0] v_count; // screen position
reg [9:0] h_count = 0; // line position
reg [9:0] v_count = 0; // screen position
// generate sync signals (active low for 640x480)
assign o_hs = ~((h_count >= HS_STA) & (h_count < HS_END));

2
vgasquare.v
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@ -29,9 +29,9 @@ module vgasquare(
vga640x480 display (
.i_pix_stb(PIXEL_CLK),
.i_rst(rst),
.o_active(VGA_ACTIVE),
.o_hs(VGA_HS),
.o_vs(VGA_VS),
.o_active(VGA_ACTIVE),
.o_x(x),
.o_y(y)
);

13
vgasquare_tb.v
View File

@ -18,16 +18,19 @@ module vgasquare_tb;
wire O_VGA_HS;
wire O_VGA_VS;
vgasquare display (
vgasquare DUT (
.PIXEL_CLK(pixel_clk), // Pixel clock: 25Mhz (or 25.125MHz) for VGA
.RST_BTN(reset), // reset button
.box_x1(10'd120),
.box_x2(10'd520),
.box_y1(9'd120),
.box_y2(9'd360),
.box_color(6'b111000), //1 bit for each color Foreground and background
.box_y1(9'd440),
.box_y2(9'd480),
.box_color(6'b100001), //1 bit for each color Foreground and background
.VGA_ACTIVE(O_VGA_ACTIVE),
.VGA_HS(O_VGA_HS), // horizontal sync output
.VGA_VS(O_VGA_VS) // vertical sync output
.VGA_VS(O_VGA_VS), // vertical sync output
.VGA_R(O_VGA_R), // 1-bit VGA red output
.VGA_G(O_VGA_G), // 1-bit VGA green output
.VGA_B(O_VGA_B) // 1-bit VGA blue output
);
endmodule // test