Added parent module

vgasquare.v

@@ -0,0 +1,52 @@
+// FPGA VGA Graphics Part 1: Top Module (static squares)
+// (C)2017-2018 Will Green - Licensed under the MIT License
+// Heavily modified by Jens True
+// Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
+
+`default_nettype none
+
+module vgasquare(
+    input wire CLK,             // board clock: 100 MHz clock in required
+    input wire RST_BTN,         // reset button
+	input wire [9:0] box_x1,
+	input wire [9:0] box_x2,
+	input wire [8:0] box_y1,
+	input wire [8:0] box_y2,    
+	input wire [2:0] box_color, //1 bit for each color 
+    output wire VGA_HS_O,       // horizontal sync output
+    output wire VGA_VS_O,       // vertical sync output
+    output wire VGA_R,    		// 1-bit VGA red output
+    output wire VGA_G,    		// 1-bit VGA green output
+    output wire VGA_B     		// 1-bit VGA blue output
+    );
+
+    wire rst = ~RST_BTN;    // reset is active low on AXI bus
+
+    // generate a 25 MHz pixel strobe
+    reg [15:0] cnt;
+    reg pix_stb;
+    always @(posedge CLK)
+        {pix_stb, cnt} <= cnt + 16'h4000;  // divide by 4: (2^16)/4 = 0x4000
+
+    wire [9:0] x;  // current pixel x position: 10-bit value: 0-1023
+    wire [8:0] y;  // current pixel y position:  9-bit value: 0-511
+
+    vga640x480 display (
+        .i_clk(CLK),
+        .i_pix_stb(pix_stb),
+        .i_rst(rst),
+        .o_hs(VGA_HS_O), 
+        .o_vs(VGA_VS_O), 
+        .o_x(x), 
+        .o_y(y)
+    );
+
+    // Draw one square
+    wire square;
+    assign square = ((x > box_x1) & (y >  box_y1) & (x < box_x2) & (y < box_y1)) ? 1 : 0; //Is box within range?
+
+
+    assign VGA_R = square ? box_color[0] : 0;       // Set R
+    assign VGA_G = square ? box_color[1] : 0  		// Set G
+    assign VGA_B = square ? box_color[2] : 0        // Set B
+endmodule