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								vga640x480.v
									
									
									
									
									
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								vga640x480.v
									
									
									
									
									
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// FPGA VGA Graphics Part 1: 640x480 60Hz VGA Driver
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// (C)2017-2018 Will Green - Licensed under the MIT License
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// Learn more at https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
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// For 60 Hz VGA i_pix_stb must be 25 MHz or 25.175 MHz
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// Details in tutorial: https://timetoexplore.net/blog/arty-fpga-vga-verilog-01
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`default_nettype none
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module vga640x480(
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    input wire i_clk,           // base clock
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    input wire i_pix_stb,       // pixel clock strobe
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    input wire i_rst,           // reset: restarts frame
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    output wire o_hs,           // horizontal sync
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    output wire o_vs,           // vertical sync
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    output wire o_blanking,     // high during blanking interval
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    output wire o_active,       // high during active pixel drawing
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    output wire o_screenend,    // high for one tick at the end of screen
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    output wire o_animate,      // high for one tick at end of active drawing
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    output wire [9:0] o_x,      // current pixel x position
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    output wire [8:0] o_y       // current pixel y position
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    );
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    // VGA timings https://timetoexplore.net/blog/video-timings-vga-720p-1080p
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    localparam HS_STA = 16;              // horizontal sync start
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    localparam HS_END = 16 + 96;         // horizontal sync end
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    localparam HA_STA = 16 + 96 + 48;    // horizontal active pixel start
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    localparam VS_STA = 480 + 11;        // vertical sync start
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    localparam VS_END = 480 + 11 + 2;    // vertical sync end
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    localparam VA_END = 480;             // vertical active pixel end
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    localparam LINE   = 800;             // complete line (pixels)
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    localparam SCREEN = 524;             // complete screen (lines)
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    reg [9:0] h_count;  // line position
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    reg [9:0] v_count;  // screen position
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    // generate sync signals (active low for 640x480)
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    assign o_hs = ~((h_count >= HS_STA) & (h_count < HS_END));
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    assign o_vs = ~((v_count >= VS_STA) & (v_count < VS_END));
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    // keep x and y bound within the active pixels
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    assign o_x = (h_count < HA_STA) ? 0 : (h_count - HA_STA);
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    assign o_y = (v_count >= VA_END) ? (VA_END - 1) : (v_count);
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    // blanking: high within the blanking period
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    assign o_blanking = ((h_count < HA_STA) | (v_count > VA_END - 1));
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    // active: high during active pixel drawing
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    assign o_active = ~((h_count < HA_STA) | (v_count > VA_END - 1)); 
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    // screenend: high for one tick at the end of the screen
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    assign o_screenend = ((v_count == SCREEN - 1) & (h_count == LINE));
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    // animate: high for one tick at the end of the final active pixel line
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    assign o_animate = ((v_count == VA_END - 1) & (h_count == LINE));
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    always @ (posedge i_clk)
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    begin
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        if (i_rst)  // reset to start of frame
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        begin
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            h_count <= 0;
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            v_count <= 0;
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        end
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        if (i_pix_stb)  // once per pixel
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        begin
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            if (h_count == LINE)  // end of line
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            begin
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                h_count <= 0;
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                v_count <= v_count + 1;
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            end
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            else 
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                h_count <= h_count + 1;
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            if (v_count == SCREEN)  // end of screen
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                v_count <= 0;
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        end
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    end
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endmodule
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