Updated userland code
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65
userland.c
65
userland.c
@ -1,3 +1,63 @@
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/******************************************************************************
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*
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* helloworld.c: simple test application
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*
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* This application configures UART 16550 to baud rate 9600.
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* PS7 UART (Zynq) is not initialized by this application, since
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* bootrom/bsp configures it to baud rate 115200
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*
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* ------------------------------------------------
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* | UART TYPE BAUD RATE |
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* ------------------------------------------------
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* uartns550 9600
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* uartlite Configurable only in HW design
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* ps7_uart 115200 (configured by bootrom/bsp)
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*/
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#include <stdio.h>
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#include "platform.h"
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#include "xil_printf.h"
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#include "xil_io.h"
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#include <simplevga.h>
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int main()
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{
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init_platform();
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print("Hello World\n\r");
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SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG0_OFFSET, 0xFFFFFFFF);
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SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG0_OFFSET, 0xFFFFFFFF);
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SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG1_OFFSET, 0xFFFFFFFF);
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SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG1_OFFSET, 0xFFFFFFFF);
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SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG2_OFFSET, 0xFFFFFFFF);
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SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG2_OFFSET, 0xFFFFFFFF);
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@ -6,6 +66,9 @@
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for(x = 1; x < 100; x++) {
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for(x = 1; x < 100; x++) {
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unsigned long xreg = ((640-x) << 16) + x;
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unsigned long xreg = ((640-x) << 16) + x;
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SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG0_OFFSET, x);
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SIMPLEVGA_mWriteReg(XPAR_SIMPLEVGA_0_S00_AXI_BASEADDR, SIMPLEVGA_S00_AXI_SLV_REG0_OFFSET, x);
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//usleep(1000000);
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sleep(1);
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}
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}
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}
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}
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cleanup_platform();
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return 0;
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}
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