685 lines
15 KiB
C
685 lines
15 KiB
C
/*
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* max7456Registers.h
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*
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* Created on: 13 oct. 2012
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* Author: Benoit
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*/
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#ifndef MAX7456REGISTERS_H_
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#define MAX7456REGISTERS_H_
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#include <Arduino.h>
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/**
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* @typedef charact
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* @brief Represents a character as stored in max7456 character memory.
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*/
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typedef byte charact[54];
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#define VM0_ADDRESS_WRITE 0x00
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#define VM0_ADDRESS_READ 0x80
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/**
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* @union REG_VM0
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* @brief Represents a Video Mode 0 Register value
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*/
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union REG_VM0
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{
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/**@brief The whole value*/
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unsigned char whole ;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief Video BUffer Enable
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* @li 0 = Enable
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* @li 1 = Disable(VOUT is high impedance)
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*/
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unsigned char videoBuffer :1;
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/**@brief Software Reset Bit
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* @li When bit set all register are set to default.
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*/
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unsigned char softwareResetBit : 1;
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/**@brief Vertical Synchronization of On-Screen Data
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* @li 0 = Enable osd immediately
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* @li 1 = Enable osd at the next ~VSYNC
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*/
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unsigned char verticalSynch : 1;
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/**@brief Enable Display of OSD Image
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* @li 0 = Off
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* @li 1 = On
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*/
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unsigned char enableOSD : 1;
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/**@brief Synch Select Mode
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* @li 0x (0 ou 1) = Autosynch select
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* @li 10 (2) = external
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* @li 11 (3) = internal
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*/
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unsigned char synchSelect : 2;
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/**@brief Video Standard Select
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* @li 0 = NTSC
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* @li 1 = PAL
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*/
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unsigned char videoSelect :1;
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/**@brief don't care*/
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unsigned char unused : 1;
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} bits;
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};
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#define VM1_ADDRESS_WRITE 0x01
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#define VM1_ADDRESS_READ 0x81
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/**@union REG_VM1
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* @brief Represents a Video Mode 1 Register value.
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*/
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union REG_VM1
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief Blinking Duty Cycle (On:Off)
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* @li b00 (0) = BT:BT
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* @li b01 (1) = BT:(2*BT)
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* @li b10 (2) = BT:(3*BT)
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* @li b11 (3) = (3*BT):BT
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*/
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unsigned char blinkingDutyCycle : 2;
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/**@brief Blinking Time (BT)
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* @li b00 (0) = 2 fields (NTSC = 33ms ; PAL = 40ms)
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* @li b01 (1) = 4 fields (NTSC = 67ms ; PAL = 80ms)
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* @li b10 (2) = 6 fields (NTSC = 100ms ; PAL = 120ms)
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* @li b11 (3) = 8 fields (NTSC = 133ms ; PAL = 160ms)
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*/
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unsigned char blinkingTime : 2;
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/**@brief Background Mode Brightness
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* @li b000 (0) = 0%
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* @li b001 (1) = 7%
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* @li b010 (2) = 14%
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* @li b011 (3) = 21%
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* @li b100 (4) = 28%
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* @li b101 (5) = 35%
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* @li b110 (6) = 43%
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* @li b111 (7) = 49%
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*/
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unsigned char backgroundModeBrightness : 3;
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/**@brief Background Mode
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* @li 0 = DMM[5] & DMM[7] sets the state of each character background
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* @li 1 = Sets all displayed background pixel to gray
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*/
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unsigned char backgroundMode : 1;
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} bits;
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};
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#define HOS_ADDRESS_WRITE 0x02
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#define HOS_ADDRESS_READ 0x82
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/**@union REG_HOS
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* @brief Represents a Horizontal Offset Register value.
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*/
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union REG_HOS
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief Vertical Position Offset
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* @li b00 0000 (0) = Farthest left (-32 pixels)
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* @li .
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* @li .
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* @li b10 0000 (32) = No horizontal offset
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* @li .
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* @li .
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* @li b11 1111 (31) = Farthest right (+31pixels)
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*/
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unsigned char horizontalPositionOffset : 6;
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/**@brief Don't care*/
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unsigned char unsused : 2;
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} bits;
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};
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#define VOS_ADDRESS_WRITE 0x03
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#define VOS_ADDRESS_READ 0x83
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/**@union REG_VOS
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* @brief Represents a Vertical Offset Register value.
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*/
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union REG_VOS
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief Vertical Position Offset
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* @li b0 0000 (0) = Farthest up (+16 pixels)
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* @li .
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* @li .
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* @li b1 0000 (16) = No vertical offset
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* @li .
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* @li .
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* @li b1 1111 (31) = Farthest down (-15 pixels)
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*/
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unsigned char verticalPositionOffset : 5;
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/**@brief Don't care*/
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unsigned char unsused : 3;
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} bits;
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};
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#define DMM_ADDRESS_WRITE 0x04
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#define DMM_ADDRESS_READ 0x84
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/**@union REG_DMM
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* @brief Represents a Display Memory Mode value.
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*/
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union REG_DMM
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief Auto-Increment Mode
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* @li 0 = Disabled
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* @li 1 = Enabled
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* @note When this bit is enabled for the first time, data in the Display Memory Address (DMAH[0] and
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DMAL[7:0]) registers are used as the starting location to which the data is written. When performing
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the auto-increment write for the display memory, the 8-bit address is internally generated, and
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therefore only 8-bit data is required by the SPI-compatible interface (Figure 21). The content is to
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be interpreted as a Character Address byte if DMAH[1] = 0 or a Character Attribute byte if
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DMAH[1] = 1. This mode is disabled by writing the escape character 1111 1111.
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If the Clear Display Memory bit is set, this bit is reset internally.
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*/
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unsigned char autoIncrementMode : 1;
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/**@brief Vertical Sync Clear (Valid only when clear display memory = 1, (DMM[2] = 1) )
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* @li 0 = Immediately applies the clear display-memory command, DMM[2] = 1
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* @li 1 = Applies the clear display-memory command, DMM[2] = 1, at the next VSYNC time
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*/
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unsigned char verticalSynchClear : 1;
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/**@brief Clear Display Memory
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* @li 0 = Inactive
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* @li 1 = Clear (fill all display memories with zeros)
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* @note This bit is automatically cleared after the operation is completed (the operation requires
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* 20us). The user does not need to write a 0 afterwards. The status of the bit can be checked by
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* reading this register.
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* This operation is automatically performed:
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* a) On power-up
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* b) Immediately following the rising edge of RESET
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* c) Immediately following the rising edge of CS after VM0[1] has been set to 1
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*/
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unsigned char clearDisplayMemory : 1;
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/**@brief Invert Bit (applies to characters written in 16-bit operating mode)
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* @li 0 = Normal (white pixels display white, black pixels display black)
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* @li 1 = Invert (white pixels display black, black pixels display white)
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*/
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unsigned char INV : 1;
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/**@brief Blink Bit (applies to characters written in 16-bit operating mode)
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* @li 0 = Blinking off
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* @li 1 = Blinking on
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* @note Blinking rate and blinking duty cycle data in the Video Mode 1 (VM1) register are used for blinking control
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*/
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unsigned char BLK : 1;
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/**@brief Local Background Control Bit (applies to characters written in 16-bit operating mode)
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* @li 0 = sets the background pixels of the character to the video input (VIN) when in external sync mode.
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* @li 1 = sets the background pixels of the character to the background mode brightness level defined by VM1[6:4] in external or internal sync mode.
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* @note In internal sync mode, the local background control bit behaves as if it is set to 1
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*/
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unsigned char LBC : 1;
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/**@brief Operation Mode Selection
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* @li 0 = 16-bit operation mode
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* @li 1 = 8-bit operation mode
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*/
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unsigned char operationModeSelection : 1;
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/**@brief Don't care*/
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unsigned char unsused : 1;
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} bits;
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};
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#define DMAH_ADDRESS_WRITE 0x05
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#define DMAH_ADDRESS_READ 0x85
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/**@union REG_DMAH
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* @brief Represents a Display Memory Address High Register value
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*/
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union REG_DMAH
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief 8th bit for Display Memory Address.
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*/
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unsigned char DisplayMemoryAdressBit8 : 1;
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unsigned char byteSelectionBit : 1;
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/**@brief Don't care*/
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unsigned char unsused : 6;
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} bits;
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};
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#define DMAL_ADDRESS_WRITE 0x06
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#define DMAL_ADDRESS_READ 0x86
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typedef unsigned char REG_DMAL;
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#define DMDI_ADDRESS_WRITE 0x07
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#define DMDI_ADDRESS_READ 0x87
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typedef unsigned char REG_DMDI;
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#define CMM_ADDRESS_WRITE 0x08
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#define CMM_ADDRESS_READ 0x88
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typedef unsigned char REG_CMM;
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#define CMAH_ADDRESS_WRITE 0x09
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#define CMAH_ADDRESS_READ 0x89
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/**@typedef REG_CMAH
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* @brief Represents a Character Memory Address HIGH value
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*/
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typedef unsigned char REG_CMAH;
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#define CMAL_ADDRESS_WRITE 0x0A
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#define CMAL_ADDRESS_READ 0x8A
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/**@typedef REG_CMAL
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* @brief Represents a Character Memory Address Low value
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*/
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typedef unsigned char REG_CMAL;
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#define CMDI_ADDRESS_WRITE 0x0B
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#define CMDI_ADDRESS_READ 0x8B
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/**@union REG_CMDI
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* @brief Represents a Character Memory Data In Register value
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*/
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union REG_CMDI
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief value of the right most pixel*/
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unsigned char rightMostPixel : 2;
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/**@brief value of the right center pixel*/
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unsigned char rightCenterPixel : 2;
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/**@brief value of the left center pixel*/
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unsigned char leftCenterPixel : 2;
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/**@brief value of the left most pixel*/
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unsigned char leftMostPixel : 2;
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} bits;
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};
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#define OSDM_ADDRESS_WRITE 0x0C
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#define OSDM_ADDRESS_READ 0x8C
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/**@union REG_OSDM
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* @brief Represents an OSD Insersion Mux Register value
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*/
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union REG_OSDM
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits
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* */
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struct
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{
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/**@brief OSD Insersion Mux Switching Time
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* @li b000 (0) : 30ns (maximum sharpness/maximum crosscolor artifacts )
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* @li b001 (1) : 35ns
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* @li b010 (2) : 50ns
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* @li b011 (3) : 75ns
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* @li b100 (4) : 100ns
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* @li b101 (5) : 120ns (minimum sharpness/minimum crosscolor artifacts)
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*/
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unsigned char osdInsertionMuxSwitchingTime : 3;
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/**@brief OSD Rise And Fall Time
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* @li b000 (0) : 20ns (maximum sharpness/maximum crosscolor artifacts )
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* @li b001 (1) : 30ns
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* @li b010 (2): 35ns
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* @li b011 (3) : 60ns
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* @li b100 (4) : 80ns
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* @li b101 (5) : 110ns (minimum sharpness/minimum crosscolor artifacts)
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*/
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unsigned char osdRiseAndFallTime : 3;
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/**@brief don't care*/
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unsigned char unused : 2;
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} bits;
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};
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#define RB0_ADDRESS_WRITE 0x10
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#define RB0_ADDRESS_READ 0x90
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#define RB1_ADDRESS_WRITE 0x11
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#define RB1_ADDRESS_READ 0x91
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#define RB2_ADDRESS_WRITE 0x12
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#define RB2_ADDRESS_READ 0x92
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#define RB3_ADDRESS_WRITE 0x13
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#define RB3_ADDRESS_READ 0x93
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#define RB4_ADDRESS_WRITE 0x14
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#define RB4_ADDRESS_READ 0x94
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#define RB5_ADDRESS_WRITE 0x15
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#define RB5_ADDRESS_READ 0x95
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#define RB6_ADDRESS_WRITE 0x16
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#define RB6_ADDRESS_READ 0x96
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#define RB7_ADDRESS_WRITE 0x17
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#define RB7_ADDRESS_READ 0x97
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#define RB8_ADDRESS_WRITE 0x18
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#define RB8_ADDRESS_READ 0x98
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#define RB9_ADDRESS_WRITE 0x19
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#define RB9_ADDRESS_READ 0x99
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#define RBA_ADDRESS_WRITE 0x1A
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#define RBA_ADDRESS_READ 0x9A
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#define RBB_ADDRESS_WRITE 0x1B
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#define RBB_ADDRESS_READ 0x9B
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#define RBC_ADDRESS_WRITE 0x1C
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#define RBC_ADDRESS_READ 0x9C
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#define RBD_ADDRESS_WRITE 0x1D
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#define RBD_ADDRESS_READ 0x9D
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#define RBE_ADDRESS_WRITE 0x1E
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#define RBE_ADDRESS_READ 0x9E
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#define RBF_ADDRESS_WRITE 0x1F
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#define RBF_ADDRESS_READ 0x9F
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/**@union REG_RBN
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* @brief Represents a Row Brithness Register value (15 of them)
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*/
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union REG_RBN
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief Character white level
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* @li b00 (0) = 120%
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* @li b01 (1) = 100%
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* @li b10 (2) = 90%
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* @li b11 (3) = 80%
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*/
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unsigned char characterWhiteLevel : 2;
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/**@brief Character black level
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* @li b00 (0) = 0%
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* @li b01 (1) = 10%
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* @li b10 (2) = 20%
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* @li b11 (3) = 20%
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*/
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unsigned char characterBlackLevel : 2;
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/**@brief don't care*/
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unsigned char unused : 4;
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} bits;
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};
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#define OSDBL_ADDRESS_WRITE 0x6C
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#define OSDBL_ADDRESS_READ 0xEC
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/**@union REG_OSDBL
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* @brief Represents an OSD Black Level Register value
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*/
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union REG_OSDBL
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief do not change those bits : factory preset*/
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unsigned char doNotChange : 4;
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/**@brief OSD Image Black Level Control.
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* @li 0 = automatic.
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* @li 1 = manual.
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*/
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unsigned char osdImageBlackLevelControl : 1;
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/**@brief don't care*/
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unsigned char unused : 3;
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} bits;
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};
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#define STAT_ADDRESS_READ 0xA0 //Read only
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/**@union REG_STAT
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* @brief Represents a Status Register value
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*/
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union REG_STAT
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief Detected PAL.
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* @li 0 = PAL signal is not detected ad VIN.
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* @li 1 = PAL signal is detected at VIN.
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*/
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unsigned char PALDetected : 1;
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/**@brief Detected NTSC.
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* @li 0 = NTSC signal is not detected ad VIN.
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* @li 1 = NTSC signal is detected at VIN.
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*/
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unsigned char NTSCDetected : 1;
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/**@brief Loos-Of-Sync.
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* @li 0 = Sunc Active. Asserted after 32 consecutive input video lines.
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* @li 1 = No Sync. Asserted after 32 consecutive missing input video lines.
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*/
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unsigned char LOS : 1;
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/**@brief ~HSYNC Ouput Level.
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* @li 0 = Active during horizontal synch time.
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* @li 1 = inactive otherwise.
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*/
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unsigned char NOTHsynchOutputLevel : 1;
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/**@brief ~VSYNC Ouput Level.
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* @li 0 = Active during vertical synch time.
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* @li 1 = inactive otherwise.
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*/
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unsigned char NOTVsynchOutputLevel : 1;
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/**@brief Character Memory Status.
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* @li 0 = Available access.
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* @li 1 = Unavailable access.
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*/
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unsigned char characterMemoryStatus : 1;
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/**@brief Reset Mode.
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* @li 0 = Clear when power up reset mode is complete.
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* @li 1 = Set when in power-up reset mode.
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*/
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unsigned char resetMode : 1;
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/**@brief don't care.*/
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unsigned char unused : 1;
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} bits;
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};
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#define DMDO_ADDRESS_READ 0xB0
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/**@typedef DMDO
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* @brief represents a Display Memory Data Out Register value.
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*/
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typedef unsigned char DMDO;
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#define CMDO_ADDRESS_READ 0xC0
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/**@union REG_CMDO
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* @brief Represents a Character Memory Data Out value.
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*/
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union REG_CMDO
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{
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/**@brief The whole register value*/
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unsigned char whole;
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/**
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* @var bits
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* @brief access to individual bits*/
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struct
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{
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/**@brief right most pixel*/
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unsigned char rightMostPowel : 2;
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/**@brief right center pixel*/
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unsigned char rightCenterPixel : 2;
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/**@brief left center pixel*/
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unsigned char leftCenterPixel : 2;
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/**@brief left most pixel*/
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unsigned char leftMostPixel : 2;
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} bits;
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};
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/**\def COLOR_BLACK
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* \brief Black value for a pixel (2bits)
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*/
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#define COLOR_BLACK 0
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/**\def COLOR_WHITE
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* \brief White value for a pixel (2bits)
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*/
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#define COLOR_WHITE 2
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/**\def COLOR_TRANSPARENT
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* \brief Transparent value for a pixel (2bits)
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*/
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#define COLOR_TRANSPARENT 1
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/**\def COLOR_GREY
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* \brief Grey value for a pixel (2bits)
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*/
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#define COLOR_GREY COLOR_TRANSPARENT
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/**@struct PIXEL
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* @brief represent a 4-pixels value
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*/
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struct PIXEL
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{
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/**@brief 4th pixel*/
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byte pix3 : 2;
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/**@brief 3rd pixel*/
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byte pix2 : 2;
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/**@brief 2nd pixel*/
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byte pix1 : 2;
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/**@brief 1st pixel*/
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byte pix0 : 2;
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};
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/**@union LINE
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* @brief Represents a line in a max7456 character ie. 12 pixels
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*/
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union LINE
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{
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/**@brief the whole line*/
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byte whole[3];
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/**@brief individual 4-pixels access*/
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struct PIXEL pixels[3];
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};
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/**
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* @union CARACT
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* @brief Represents a character with lines and pixels.
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* example : myCarac.line[3].pixels[2].pix2 = COLOR_TRANSPARENT ;
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*/
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union CARACT
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{
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/**@brief the whole CARACT as in max7456 Character Memory*/
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charact whole;
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/**@brief acces with lines*/
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union LINE line[18];
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};
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enum{
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_BT_BT=0,
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_BT_2BT,
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_BT_3BT,
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_3BT_BT
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};
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enum{
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_2fields=0,
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_4fields,
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_6fields,
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_8fields
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};
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#endif /* MAX7456REGISTERS_H_ */
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